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This module interfaces with a DP83223 and brings its signals into the local
clock domain. It uses 4x oversampling and determines an appropriate sample using
the techniques described in Xilinx
XAPP225 to select an appropriate sample. The specific implementation is a bit
different since we use a 250 Mhz clock with a DDR FF (as opposed to four 125 MHz
clocks in quadrature) and the selection process is split over several clock
cycles. While most cycles will produce one bit of data, occasionally zero or two
bits will be produced, due to differences in frequency between the local and far
ends. This is a disadvantage when compared to a PLL-based solution, as the
entire rest of the data path up to the PCS (when we can finally align the data)
must handle these edge cases. However, it avoids the internal,
nebulously-specified, and limited-in-number iCE40 PLLs.
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